From what I remember one of problems with CISC is that it has variable length instructions and these are harder to predict since you have to analyze all instructions up to the current one wheres for RISC you exactly know where is each instruction in memory/cache.
one of problems with CISC is that it has variable length instructions
RISC systems also have variable length instructions, they’re just a bit stricter with the implementation that alleviates a lot of the issues (ARM instructions are always either 16-bits or 32-bits, while RISC-V is always a multiple of 16-bits and self-describing, similar to UTF-8)
Edit: Oh, and ARM further restricts instruction length based on a CPU flag, so you can’t mix and match at an instruction level. It’s always one or the other, or it’s invalid.
I was thinking about Apple’s M CPUs that have fixed length and they benefit out of it. It was explained on Anandtech years ago, here is a brief paragraph on the topic. Sadly Anandtech article(s) isn’t available anymore.
Since this type of chip has a fixed instruction length, it becomes simple to load a large number of instructions and explore opportunities to execute operations in parallel. This is what’s called out-of-order execution, as explained by Anandtech in a highly technical analysis of the M1. Since complex CISC instructions can access memory before completing an operation, executing instructions in parallel becomes more difficult in contrast to the simpler RISC instructions.
Ahh, yep it turns out ARM actually removed Thumb support with their 64-bit transition, so their instruction length is fixed now, and Thumb never made it into the M* SoCs.
This isn’t completely true. Even a basic instruction like ADD has multiple implementations depending on the memory sources.
For example, if the memory operand is in RAM, then the ADD needs to be decoded to include a fetch before the actual addition. RISC doesn’t change that fact.
Yes, but RISC knows the exact position of that instruction in cache and how many instructions fit the instructions cache or pipeline. Like you said, it doesn’t help with data cache.
Are you sure there’s a significant difference between RISC and CISC after instructions are decoded?
The assembly in RISC is just an abstraction of the machine code, as it also is in CISC. If the underlying CPU has the same capabilities then it doesn’t really matter what the assembly looks like?
Of course, the underlying CPUs aren’t the same and that’s the real point of differentiation.
From what I remember one of problems with CISC is that it has variable length instructions and these are harder to predict since you have to analyze all instructions up to the current one wheres for RISC you exactly know where is each instruction in memory/cache.
RISC systems also have variable length instructions, they’re just a bit stricter with the implementation that alleviates a lot of the issues (ARM instructions are always either 16-bits or 32-bits, while RISC-V is always a multiple of 16-bits and self-describing, similar to UTF-8)
Edit: Oh, and ARM further restricts instruction length based on a CPU flag, so you can’t mix and match at an instruction level. It’s always one or the other, or it’s invalid.
I was thinking about Apple’s M CPUs that have fixed length and they benefit out of it. It was explained on Anandtech years ago, here is a brief paragraph on the topic. Sadly Anandtech article(s) isn’t available anymore.
Ahh, yep it turns out ARM actually removed Thumb support with their 64-bit transition, so their instruction length is fixed now, and Thumb never made it into the M* SoCs.
This isn’t completely true. Even a basic instruction like ADD has multiple implementations depending on the memory sources.
For example, if the memory operand is in RAM, then the ADD needs to be decoded to include a fetch before the actual addition. RISC doesn’t change that fact.
Yes, but RISC knows the exact position of that instruction in cache and how many instructions fit the instructions cache or pipeline. Like you said, it doesn’t help with data cache.
Are you sure there’s a significant difference between RISC and CISC after instructions are decoded?
The assembly in RISC is just an abstraction of the machine code, as it also is in CISC. If the underlying CPU has the same capabilities then it doesn’t really matter what the assembly looks like?
Of course, the underlying CPUs aren’t the same and that’s the real point of differentiation.
See my other reply